Next Generation Metrology and Inspection

Thu, Nov 21, 2013 2:01 PM EST

  

Next Generation Metrology and Inspection

Continued scaling and more complex device structures, including FinFETs and 3D stacking, are creating new challenges in metrology and inspection. Smaller defects but be detected and analyzed on an increasingly diverse set of materials. Chip makers are looking for better wafer edge inspection techniques, higher resolution metrology tools, 450mm-capability and new compositional analysis solutions. Experts will describe new approaches for next generation metrology and inspection, including measurements of CDs, stress, film thickness and non-visual defects. 

  Speakers:

Alain Diebold, CNSE

Alain Diebold is Empire Innovation Professor of Nanoscale Science and Executive Director, Center for Nanoscale Metrology at the SUNY College of Nanoscale Science and Engineering.  He is a fellow of the American Vacuum Society and SPIE as well as a senior member of the IEEE. In addition to the Handbook of Silicon Semiconductor Metrology (Dekker, New York, 2001), Professor Diebold has published more than 70 journal articles, more than 100 conference proceedings, and presented more than 85 invited talks. He is an associate editor for IEEE’s Transactions on Semiconductor Manufacturing. He has served as chair of the ITRS Metrology Technical Working Group since its inception.

 

Michael Lercel, SEMATECH

Michael Lercel is SEMATECH's senior director of Nanodefectivity and Metrology. In this role he is responsible for leading both SEMATECH’s Metrology Program and Nanodefect Center, which are dedicated to understanding defect generation processes and developing effective mitigation strategies and solutions to component-level defect challenges. Prior to joining SEMATECH, Lercel was senior director of EUV product marketing at Cymer, where he was responsible for EUV source product roadmaps. Preceding that, Lercel served in various lithography and process-related positions at IBM for 14 years, most recently as Strategic Equipment Council manager.

While on assignment from IBM, Lercel served as SEMATECH’s director of Lithography from 2005-2008, spearheading the development of various lithography options such as 193 nm high-index immersion, double patterning, and extreme ultraviolet lithography (EUVL), as well as alternative technologies such as nanoimprint and maskless.

 

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